I. Field of the Invention.
The present invention relates generally to latches and flip-flops, and more particularly relates to a flip-flop capable of suppressing and compensating for metastable conditions.
II. Description of the Related Art.
Flip-flops are often used by system designers to synchronize signals operating at different frequencies to a local clock. However, since the signals are asynchronous to the local clock, the setup and hold time specifications associated with the flip-flop are sure to be violated. When the setup and hold time is violated, the output response of the flip-flop is uncertain. The output may assume a "metastable" state, defined as the time period during which the output of a digital logic device is not at logic level 1 or logic level 0, but instead resides at an output level between logic level 0 and logic level 1. The voltage ranges corresponding to different logic levels are specified by the manufacturer of the device. For bipolar TTL technology, for example, the metastable region might lie between 0.8 volts and 2.0 volts.
The metastable problem occurs when the signal being input to the flip-flop is undergoing a transition from one logic level to the other simultaneously with the active edge of the local clock pulse, causing the latch section of the flip-flop to latch at an intermediate voltage level. Since the input data is changing while it is being clocked, the system designer does not care if the flip-flop goes to either a high or low logic level in this instance, just so long as the output does not "hang-up" in the metastable region. Neither level would be valid since the setup and hold was violated; so the actual result in this case is immaterial. Eventually, the output of the flip-flop will stabilize at a valid logic level; however, logic circuitry following the flip-flop depends upon the delay specification (stated time period from the clock pulse to a valid output) being met. A metastable output may cause this logic circuitry to fail. Thus, the metastable characteristics of the flip-flop used to synchronize an asynchronous data stream can influence overall system reliability.
Therefore, a need has arisen for a flip-flop which corrects for metastable output conditions.